A Distributed Three-hop Routing Protocol to Increase the
Capacity of Hybrid
Wireless Networks
ABSTRACT
Hybrid
wireless networks combining the advantages of both mobile ad-hoc networks and
infrastructure wireless networks have been receiving increased attention due to
their ultra-high performance. An efficient data routing protocol is important
in such networks for high network capacity and scalability. However, most
routing protocols for these networks simply combine the ad-hoc transmission
mode with the cellular transmission mode, which inherits the drawbacks of
ad-hoc transmission. This paper presents a Distributed Three-hop Routing
protocol (DTR) for hybrid wireless networks. To take full advantage of the
widespread base stations, DTR divides a message data stream into segments and
transmits the segments in a distributed manner. It makes full spatial reuse of
a system via its high speed ad-hoc interface and alleviates mobile gateway
congestion via its cellular interface. Furthermore, sending segments to a
number of base stations simultaneously increases throughput and makes full use
of widespread base stations. In addition, DTR significantly reduces overhead
due to short path lengths and the elimination of route discovery and
maintenance. DTR also has a congestion control algorithm to avoid overloading
base stations. Theoretical analysis and simulation results show the superiority
of DTR in comparison with other routing protocols in terms of throughput
capacity, scalability and mobility resilience. The results also show the
effectiveness of the congestion control algorithm in balancing the load between
base stations.
EXISTING SYSTEM


PROPOSED SYSTEM




System Architecture

ALGORITHM:
v Load Balancing Algorithm


v Wireless Network


v Congestion Control Algorithm

v DTR



MODULE DESCRIPTION
Ø Load-Balancing
Ø DTR
Ø Wireless Network
Load-Balancing:
Interflow packet order is natively preserved
besetting slicing threshold to the delay upper bound at .Any two packets in the
same flow slice cannot be disordered as they are dispatched to the same
switching path where processing is
guaranteed; and two packets in the same flow but different flow slices will be
in order at departure, as the earlier packet will have depart from before the latter
packet arrives. Due to the fewer number of active flow slices, the only
additional overhead in, the hash table, can be kept rather small, , and placed
on-chip to provide ultrafast access speed. This table size depends only on
system line rate and will stay unchanged even if scales to more than thousand
external ports, thus guarantees system scalability.
DTR:
Through lay-aside Buffer Management module, all
packets are virtually queued at the output according to the flow group and the
priority class in a hierarchical manner. The output scheduler fetches packets
to the output line using information provided by. Packets in the same flow will
bevirtually buffered in the same queue and scheduled in discipline. Hence,
intraflow packet departure orders holdas their arriving orders at the multiplexer.
Central-stage parallel switches adopt an output-queued model. By Theorem, we
derive packet delay bound at firststage. We then study delay at second-stage
switches. Define native packet delay at stage m of an be delay experienced at
stage m on the condition that all the preceding stages immediately send all
arrival packets out without delay.
Wireless Network:
We consider the Multistage Multiplane
Clos-networkbased switch by Chao et a . It is constructed of five stages of
switchmodules with top-level architecture similar to a external input/output
ports. The first and last stages Clos are composed of input demultiplexers and output multiplexers,
respectively, having similar internal structures as those in PPS. Stages 2-4 of
M2Clos are constructed by parallel switching planes; however, each plane is no
longer formed by a basic switch, but by
a three-stage Clos Network to support large port count. Inside each Clos
Network, the first stage is composed by k identical Input Modules. Each IM is
an packet switch, with each output link connected to a Central Module. Thus,
there are a total of m identical in second stage of the Close networks.
SYSTEM SPECIFICATION
Hardware Requirements:
v System : Pentium IV 2.4 GHz.
v Hard Disk
: 40 GB.
v Floppy Drive :
1.44 Mb.
v Monitor
: 14’ Colour Monitor.
v Mouse : Optical Mouse.
v Ram :
512 Mb.
Software Requirements:
v Operating system : Windows 7 Ultimate.
v Coding Language : ASP.Net with C#
v Front-End : Visual Studio 2010 Professional.
v Data Base : SQL Server 2008.
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