IEEEE 2014 VLSI
COMPLETED PROJECTS-
1 A Super regenerative QPSK Receiver
2 Defense Against Primary User
Emulation Attacks in Cognitive Radio Networks Using Advanced
Encryption
Standard
3 Analysis and Design of a
Low-Voltage Low-Power Double-Tail Comparator (micro wind)
4 Efficient VLSI Implementation of
Neural Networks With HyperbolicTangent Activation
Function
5 Efficient Algorithm and
Architecture for Elliptic Curve Cryptography for Extremely Constrained
Secure
Applications
6 A Method to Extend Orthogonal
Latin Square Codes
7 Increase in Read Noise Margin of
Single-Bit-Line SRAM Using A diabatic Change of Word Line
Voltage
8 Efficient Integer Dct
Architectures For Hevc
9 Precise VLSI Architecture for AI
Based 1-D/ 2-D Daub-6 Wavelet Filter Banks With Low Adder-
Count
10 Simplifying Clock Gating Logic by
Matching Factored Forms
11 Sensitization Input Vector Impact on
Propagation Delay for Nanometer
CMOS
ICs: Analysis and Solutions
12 Non binary LDPC Decoder Based on
Simplified Enhanced Generalized Bit-Flipping
Algorithm
13 An Optimized Modified Booth Recorder for Efficient Design of the Add-
Multiply Operator
14 Eliminating Synchronization Latency
Using Sequenced Latching
15 Efficient Implementation of
Reconfigurable Warped Digital Filters With Variable Low-Pass, High-
Pass,
Band pass, and Band stop Responses
16 Novel Circuit-Level Model for Gate
Oxide Short and its Testing Method in SRAMs(micro wind)
17 High-Throughput Multi standard
Transform Core Supporting MPEG/H.264/VC-1 Using Common
Sharing
Distributed Arithmetic
18 Software/Hardware Parallel
Long-Period Random Number Generation Framework Based on the
WELL
Method
19 Recursive Approach to the Design of a
Parallel Self-Timed Adder.
20 Multi-Zone Digital Crosstalk
Reduction by Image Processing in 3D Display
21 A Multichannel Oscillator for a
Resonant Chemical Sensor System
22 A 5.8-GHz Wideband TSPC
Divide-by-16/17. Dual Modulus Prescaler.
23 Fast Sign Detection Algorithm for the
RNS Moduli Set {2n+1 − 1, 2n − 1, 2n}
24 Multifunction Residue Architecture
for Cryptography
25 Design of Efficient Binary
Comparators in Quantum-Dot Cellular Automata
26 Aging-Aware Reliable Multiplier
Design With Adaptive Hold Logic
27 Area-Delay Efficient Binary Adders in
QCA
28 Area–Delay–Power Efficient Carry
Select Adder
29 Low-Complexity Hardware Design for
Fast Solving LSPs with Coordinated Polynomial Solution
30 Fast Design Optimization Through
Simple Kriging Metamodeling: A Sense Amplifier Case Study
31 Fully Reused VLSI Architecture of.
FM0/Manchester Encoding Using SOLS.Technique for DSRC
Applications.
32. Input Vector Monitoring Concurrent BIST
Architecture Using SRAM Cells
